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?2015 ds-20005015b 08/15 not recommended for new designs www.microchip.com 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 features ? organized as 4m x16 ? single voltage read and write operations ? 2.7-3.6v ? superior reliability ? endurance: 100,000 cycles minimum ? greater than 100 years data retention3 ? low power consumption (typical values at 5 mhz) ? active current: 4 ma (typical) ? standby current: 3 a (typical) ? auto low power mode: 3 a (typical) ? 128-bit unique id ? security-id feature ? 256 word, user one-time-programmable ? protection and security features ? hardware boot block protection/wp# input pin, uni- form (32 kword) and non-uniform (8 kword) options available ? user-controlled individual block (32 kword) protection, using software only methods ? password protection ? hardware reset pin (rst#) ? fast read and page read access times: ? 90 ns read access time ? 25 ns page read access times - 4-word page read buffer ? latched address and data ? fast erase times: ? sector-erase time: 18 ms (typical) ? block-erase time: 18 ms (typical) ? chip-erase time: 40 ms (typical) ? erase-suspend/-resume capabilities ? fast word and write-buffer programming times: ? word-program time: 7 s (typical) ? write buffer programming time: 1.75 s / word (typical) - 16-word write buffer ? automatic write timing ? internal v pp generation ? end-of-write detection ? toggle bits ? data# polling ? ry/by# output ? cmos i/o compatibility ? jedec standard ? flash eeprom pinouts and command sets ? cfi compliant ? packages available ? 48-lead tsop ? 48-ball tfbga ? all devices are rohs compliant the sst38vf6401/6402/6403/6404 are 4m x1 6 cmos advanced multi-purpose flash plus (advanced mpf+) devices manuf actured with proprietary, high-perfor- mance cmos super- flash technology. th e split-gate cell design and thick-oxide tunneling injector attain better reliabi lity and manufacturability compared with alternate approaches. the sst38vf 6401/6402/6403/6404 write (program or erase) with a 2.7-3.6v power supply. this device conforms to jedec standard pin assignments for x16 memories. not recommended for new designs. please use sst38vf6401 b/6402b/6403b/64040b downloaded from: http:///
?2015 ds-20005015b 08/15 2 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs product description the sst38vf6401, sst38vf6402, sst38vf6403, and sst38vf6404 devices are 4m x16 cmos advanced multi-purpose flash plus (advanced mpf+ ) manufactured with proprietary, high-perfor- mance cmos superflash technology. the split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. the sst38vf6401/ 6402/6403/6404 write (program or erase) with a 2.7-3.6v power supply. these devices conform to jedec standard pin assignments for x16 memories. featuring high performance word-program, the sst38vf6401/6402/6403 /6404 provide a typical word- program time of 7 sec. for faster word-programming performance, the write-buff er programming feature, has a typical word-program time of 1.75 sec. these devices use toggle bit or data# polling to indicate program operation completion. in addition to single-word read, advanced mpf+ devices provide a page-read feature that enables a faster word read time of 25 ns, for words on the same page. to protect against inadvertent write, the sst38vf6401/6402/6403/6404 have on-chip hardware and software data protection schemes. designed, manufactured, and tested for a wide spectrum of appli- cations, these devices are available with 100,000 cycles minimum endurance. data retention is rated at greater than 100 years. the sst38vf6401/6402/6403/6404 are suited for applications that require the convenient and e conom- ical updating of program, configuration, or data memory. for all system applications, advanced mpf+ significantly improve performance and reliability, while lowering power consumption. these devices inherently use less energy during erase and progra m than alternative flash technologies. the total energy consumed is a function of the applied voltage, current, and time of application. for any gi ven voltage range, the superflash technology uses less current to program and has a shorter erase time; therefore, the total energy consumed during any erase or program operation is less than alternativ e flash technologies. these devices also improve flexibility while lowering the cost for program, data, and configuration stor- age applications. the superflash technology provides fixed erase and program times, independent of the number of erase/program cycles that have occurred. therefore, the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and program times increase with accumulated erase/program cycles. the sst38vf6401/6402/6403/6404 also offer flexible data protection features. applications that require memory protection from program and erase operations can use the boot block, individual block protection, and advanced protection features. for applications that require a permanent solu- tion, the irreversible block locking feature provides permanent protection for memory blocks. to meet high-density, surface mount requirements, the sst38vf6 401/6402/6403/6404 devices are offered in 48-lead tsop and 48-ball tfbga packages. see figures 2 and 3 for pin assignments and table 1 for pin descriptions. downloaded from: http:///
?2015 ds-20005015b 08/15 3 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs functional block diagram figure 1: functional block diagram y-decoder i/o buffers and data latches 1309 b1.1 address buffer & latches x-decoder dq 15 - dq 0 memory address oe# ce# we# superflash memory control logic wp# reset# ry/by# downloaded from: http:///
?2015 ds-20005015b 08/15 4 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs pin assignments figure 2: pin assignments for 48-lead tsop figure 3: pin assignments for 48-ball tfbga a15a14 a13 a12 a11 a10 a9a8 a19a20 we# rst# a21 wp# ry/by# a18a17 a7a6 a5 a4 a3 a2 a1 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a16nc v ss dq15dq7 dq14 dq6 dq13 dq5 dq12 dq4 v dd dq11dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# v ss ce#a0 4847 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1309 48-tsop p1.0 standard pinout top view die up 1309 48-tfbga p1.0 a b c d e f g h 65 4 3 2 1 top view (balls facing down) a13 a9 we# ry/by# a7a3 a12 a8 rst# wp# a17 a4 a14a10 a21 a18 a6a2 a15a11 a19 a20 a5a1 a16 dq7dq5 dq2 dq0 a0 nc dq14dq12 dq10 dq8 ce# dq15dq13 v dd dq11 dq9 oe# v ss dq6dq4 dq3 dq1 v ss downloaded from: http:///
?2015 ds-20005015b 08/15 5 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs table 1: pin description symbol pin name functions a ms 1 -a 0 address inputs to provide memory addresses. during sector-erase a ms -a 12 address lines will select the sector. during block-erase a ms -a 15 address lines will select the block. dq 15 -dq 0 data input/output to output data during read cycles and receive input data during write cycles. data is internally latched during a write cycle. the outputs are in tri-state when oe# or ce# is high. wp# write protect to protect t he top/bottom boot block from erase/program operation when grounded. ry/by# ready/busy to indicate when the device is actively programming or erasing. rst# reset to reset and return the device to read mode. ce# chip enable to activate the device when ce# is low. oe# output enable to gate the data output buffers. we# write enable to control the write operations. v dd power supply to provide power supply voltage: 2.7-3.6v v ss ground nc no connection unconnected pins. t1.0 20005015 1. a ms = most significant address a ms = a 21 for sst38vf6401/6402/6403/6404 downloaded from: http:///
?2015 ds-20005015b 08/15 6 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs memory maps table 2: sst38vf6401and sst38vf6402 memory maps sst38vf6401 block 1,2 1. each block, b0-b127 is 32kword. 2. each block consists of eight sectors. sectors 3 3. each sector, s0-s1023 is 4kword. address a 21 -a 12 4 4. x = 0 or 1. block address (ba) = a 21 - a 15 ; sector address (sa) = a 21 - a 12 vpb 5 5. each block has an associated vpb and nvpb. nvpb 5 wp# 6 6. block b0 is the boot block. b0 6 s0-s7 0000000xxx yes yes yes b1 s8-s15 0000001xxx yes yes no b2 s16-s23 0000010xxx yes yes no b3 s24-s31 0000011xxx yes yes no b4 s32-s39 0000100xxx yes yes no b5 s40-s47 0000101xxx yes yes no b6 s48-s55 0000110xxx yes yes no b7 s56-s63 0000111xxx yes yes no b8 - b119 follow the same pattern b120 s960-s967 1111000xxx yes yes no b121 s968-s975 1111001xxx yes yes no b122 s976-s983 1111010xxx yes yes no b123 s984-s991 1111011xxx yes yes no b124 s992-s999 1111100xxx yes yes no b125 s1000-s1007 1111101xxx yes yes no b126 s1008-s1015 1111110xxx yes yes no b127 s1016-s1023 1111111xxx yes yes no sst38vf6402 block 1,2 sectors 3 address a 21 -a 12 4 vpb 5 nvpb 5 wp# 7 7. block b127 is the boot block. b0 s0-s7 0000000xxx yes yes no b1 s8-s15 0000001xxx yes yes no b2 s16-s23 0000010xxx yes yes no b3 s24-s31 0000011xxx yes yes no b4 s32-s39 0000100xxx yes yes no b5 s40-s47 0000101xxx yes yes no b6 s48-s55 0000110xxx yes yes no b7 s56-s63 0000111xxx yes yes no b8 - b119 follow the same pattern b120 s960-s967 1111000xxx yes yes no b121 s968-s975 1111001xxx yes yes no b122 s976-s983 1111010xxx yes yes no b123 s984-s991 1111011xxx yes yes no b124 s992-s999 1111100xxx yes yes no b125 s1000-s1007 1111101xxx yes yes no b126 s1008-s1015 1111110xxx yes yes no b127 7 s1016-s1023 1111111xxx yes yes yes t2.0 20005015 downloaded from: http:///
?2015 ds-20005015b 08/15 7 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs table 3: sst38vf6403and sst38vf6404 memory maps (1 of 2) sst38vf6403 block 1,2 sectors 3 address a 21 -a 12 4 vpb 5 nvpb 5 wp# 6 b0 5,6 s0 0000000000 yes yes yes s1 0000000001 yes yes yes s2 0000000010 yes yes no s3 0000000011 yes yes no s4 0000000100 yes yes no s5 0000000101 yes yes no s6 0000000110 yes yes no s7 0000000111 yes yes no b1 s8-s15 0000001xxx yes yes no b2 s16-s23 0000010xxx yes yes no b3 s24-s31 0000011xxx yes yes no b4 s32-s39 0000100xxx yes yes no b5 s40-s47 0000101xxx yes yes no b6 s48-s55 0000110xxx yes yes no b7 s56-s63 0000111xxx yes yes no b8 - b119 follow the same pattern b120 s960-s967 1111000xxx yes yes no b121 s968-s975 1111001xxx yes yes no b122 s976-s983 1111010xxx yes yes no b123 s984-s991 1111011xxx yes yes no b124 s992-s999 1111100xxx yes yes no b125 s1000-s1007 1111101xxx yes yes no b126 s1008-s1015 1111110xxx yes yes no b127 s1016-s1023 1111111xxx yes yes no sst38vf6404 block 1,2 sectors 3 address a 21 -a 12 4 vpb 5 nvpb 5 wp# 7 b0 s0-s7 0000000xxx yes yes no b1 s8-s15 0000001xxx yes yes no b2 s16-s23 0000010xxx yes yes no b3 s24-s31 0000011xxx yes yes no b4 s32-s39 0000100xxx yes yes no b5 s40-s47 0000101xxx yes yes no b6 s48-s55 0000110xxx yes yes no b7 s56-s63 0000111xxx yes yes no b8 - b119 follow the same pattern b120 s960-s967 1111000xxx yes yes no b121 s968-s975 1111001xxx yes yes no b122 s976-s983 1111010xxx yes yes no b123 s984-s991 1111011xxx yes yes no b124 s992-s999 1111100xxx yes yes no downloaded from: http:///
?2015 ds-20005015b 08/15 8 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs b125 s1000-s1007 1111101xxx yes yes no b126 s1008-s1015 1111110xxx yes yes no block 1,2 sectors 3 address a 21 -a 12 4 vpb 5 nvpb 5 wp# 7 b127 5 , 7 s1016 1111111000 yes yes no s1017 1111111001 yes yes no s1018 1111111010 yes yes no s1019 1111111011 yes yes no s1020 1111111100 yes yes no s1021 1111111101 yes yes no s1022 1111111110 yes yes yes s1023 1111111111 yes yes yes t3.0 20005015 1. each block, b0-b127 is 32kword. 2. each block consists of eight sectors. 3. each sector, s0-s1023 is 4kword. 4. x = 0 or 1. block address (ba) = a 21 - a 15 ; sector address (sa) = a 21 - a 12 5. each block has an associated vpb and nvpb, except for some blocks in sst39vf6403 and sst39vf6404. in sst39vf6403, block b0 does not have a single vpb or nvpb for all 32 kwords. instead, each sector (4 kword) in block b0 has its own vpb and nvpb. in sst39vf6404, block b127 does not have a single vpb or n vpb for all 32 kwords. instead, each sector (4 kword) in block b127 has its own vpb and nvpb. 6. the 8kword boot block consists of s0 and s1 in block b0. 7. the 8kword boot block consists of s1022 and s1023 in block b127. table 3: sst38vf6403and sst38vf6404 memory maps (continued) (2 of 2) downloaded from: http:///
?2015 ds-20005015b 08/15 9 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs device operation the memory operations functions of these devices are initiated using commands written to the device using standard microprocessor write sequences. a command is written by asserting we# low while keeping ce# low. the address bus is latched on the falling edge of we# or ce#, whichever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first. the sst38vf6401/6402/6403/6404 also have the auto low power mode which puts the d evice in a near-standby mode after data has been accessed with a valid read operation. this reduces the i dd active read current from typically 4 ma to typically 3 a. the auto low power mode reduces the typical i dd active read current to the range of 2 ma/mhz of read cycle time. the device requires no access time to exit the auto low power mode after any address transition or control signal transition used to initiate another read cycle. the device does not enter auto-low power mode after power-up with ce# held steadily low, until the first address transition or ce# is driven high. read the read operation of the sst38vf6401/6402/6403/6404 is controlled by ce# and oe#, bot h of which have to be low for the system to obtain data from the outputs. ce# is used for device selection. when ce# is high, the chip is deselected and only standby power is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either ce# or oe# is high. refer to figure 5, the read cycle timing diagram, for further details. page read the page read operation utilizes an asynchronous method that enables the system to read data from the sst38vf6401/6402/6403/6404 at a faster rate. this operation allows users to read a four-word page of data at an average speed of 41.25 ns per word. in page read, the initial word read from the page requires t acc to be valid, while the remaining three words in the page require only t pac c . all four words in the page have the same address bits, a 21 -a 2 , which are used to select the page. address bits a 1 and a 0 are toggled, in any order, to read the words within the page. the page read operation of the sst38vf6401/6402/6403/6404 is controlled by ce# and oe#. both ce# and oe# must be low for the system to obtain data from the output pins. ce# controls device selection. when ce# is high, the chip is deselected and only standby power is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either ce# or oe# is high. refer to figure 6, the page read cycle timing diagram, for further details. word-program operation the sst38vf6401/6402/6403/6404 can be programmed on a word-by-word basis. bef ore program- ming, the sector where the word exists must be fully erased. the program operation is accomplished in three steps. the first step is the three-byte load sequence for software data protection. the second step is to load word address and word data. during the word-program operation, the addresses a re latched on the falling edge of either ce# or we#, whichever occurs las t. the data is latched on the ris- ing edge of either ce# or we#, whichever occurs first. the third step is the internal program operation which is initiated after the rising edge of the four th we# or ce#, whichever occurs first. the program operation, once initiat ed, will be completed within 10 s. see figures 7 and 8 for we# and ce# con- trolled program operation timing diagrams and figure 24 for flowcharts. downloaded from: http:///
?2015 ds-20005015b 08/15 10 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs during the program operat ion, the only valid reads are data# polling, toggle bits, and ry/by#. during the internal program operation, the host is free to perform additional tasks. any commands issued during the internal program operation are ignored. during the command sequence, wp# should be statically held high or low. when programming more than a few words, microchip recommends write-buffer programming. write-buffer programming the sst38vf6401/6402/6403/6404 offer write-buffer programming, a feature that enables faster effective word programming. to use this feature, write up to 16 words with the write-to-buffer co m- mand, then use the program buffer-to-flash command to program the write-buffer to memory. the write-to-buffer command consists of between 5 and 20 write cycles. the total number of write cycles in the write-to-buffer command sequence is equal to the number of words to be written to the buffer plus four. the first three cycles in the command sequence tell the device that a write-to-buffer operation will begin. the fourth cycle tells the device the number of words to be written into the buffer and the bloc k address of these words. specifically, the write cycle consis ts of a block address and a data value called the word count (wc), which is the number of words to be written to the buffer minus one. if the wc is greater than 15, the maximum buffer size minus 1, then the operation aborts. for the fifth cycle, and all subsequent cycles of the write-to-buffer command, the command sequence consists of the addresses and data of the words to be written into the buffer. all of these cycles mu st have the same a 21 - a 4 address, otherwise the operation aborts. the number of write cycles required is equal to the number of words to be written into the write-buffer, which is equal to wc plus one. the correct number of write cycles must be issued or the operation will abort. each write cycle decre- ments the write-buffer counter, even if two or more of the write cycles have identical address values. only the final data loaded for each buffer location is held in the write-buffer. once the write-to-buffer command sequence is completed, the program buffer-to-flash command should be issued to program the write-buffer contents to the specified block in memory. the block address (i.e. a 21 - a 15 ) in this command must match the block address in the 4th write cycle of the write-to-buffer command or the operation aborts. see table 11 for details on write-to-buffe r and pro- gram-buffer-to-flash commands. while issuing these command sequences, the write-buffer programming abort detection bit (dq1) indicates if the operation has aborted. there are several cases in which the device can abort: ? in the fourth write cycle of the write-to-buffer command, if the wc is greater than 15, the opera- tion aborts. ? in the fifth and all subsequent cycles of the write-to-buffer command, if the address values, a 21 - a 4 , are not identical, the operation aborts. ? if the number of write cycles between the fifth to the last cycle of the write-to-buffer command is greater than wc +1, the operation aborts. ? after completing the write-to-buffer command sequence, issuing any command other than the program buffer-to-flash command, aborts the operation. ? loading a block address, i.e. a 21 -a 15, in the program buffer-to-flash command that does not match the block address used in the write-to-buffer command aborts the operation. downloaded from: http:///
?2015 ds-20005015b 08/15 11 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs if the write-to-buffer or program buffer-to-flash operation aborts, then dq 1 = 1 and the device enters write-buffer-abort mode. to execute another operation, a write-to-buffer abort-reset command mu st be issued to clear dq 1 and return the device to standard read mode. after the write-to-buffer and program buffer-to-flash commands are successfully issued, the pro- gramming operation can be monitored usin g data# polling, toggle bits, and ry/by#. sector/block-erase operations the sector-erase and block-erase operations allo w the system to erase the device on a sector-by- sector, or block-by-block, basis. the sst38vf6401/6402/6403/6404 offer both sector-erase and block- erase modes. the sector-erase architecture is based on a sector size of 4 kwords. the sector-erase command can erase any 4 kword sector (s0 - s1023). the block-erase architecture is based on block size of 32 kwords. in sst38vf6401 and sst38vf6402 devices, the block-erase command c an erase any 32kword block (b0-b127). for the non-uniform boot block devices, sst38vf6403 and sst38vf6404, the block-erase command can erase any 32 kword block except the block that contains the boot area. in the boot area, block-erase behaves like sector-erase, and only erases a 4kword sector. for the sst38vf6403 device, a block- erase executed on the boot block (b0), will result in the device erasing a 4kword sect or in b0 located at a 21 -a 12 . for the sst38vf6404 device, a block-erase exec uted on the boot bl ock (b127), will result in the device erasing a 4kword sector in b127 located at a 21 -a 12 . the sector-erase operation is initiated by executing a six-byte command sequence with sector-erase command (50h) and sector address (sa) in the last bus cycle. the block-erase operation is initiated by executing a six-byte command sequence with block-erase command (30h) and block address (ba) in the last bus cycle. the sector or block address is latched on the falling edge of the sixth we# pulse, while the command (50h or 30h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. the end-of-erase operation can be determined using either data# polling or toggle bit methods. the ry/by# pin ca n also be used to monitor the erase operation. for more information, see figures 14 and 15 for timing waveforms and figure 29 for the flowchart. any commands, other than erase-suspend, issued during the sector- or block-erase operation are ignored. a ny attempt to sector- or block-erase memory inside a block protected by volatile block pro- tection, non-volatile block prot ection, or wp# (low) will be ignore d. during the command sequence, wp# should be statically held high or low. erase-suspend/erase-resume commands the erase-suspend operation temporarily suspends a sector- or block-erase operation thus allowing data to be read or programmed into any sector or block that is not engaged in an erase operation. the operation is executed with a one-byte command sequence with erase-suspend command (b0h). the device automatically enters read mode within 20 s (max) after the erase-suspend command had been issued. valid data can be read, using a read or page read operation, from any sector or block that is not being erased. reading at an address location within erase-suspended sectors or blocks will output dq 2 toggling and dq 6 at ?1?. while in erase-suspend, a word-program or write-buffer pro- gramming operation is allowed anywhere except the sector or block selected for erase-suspend. downloaded from: http:///
?2015 ds-20005015b 08/15 12 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs to resume a suspended sector-erase or block-erase operation, the system must issue the erase- resume command. the operation is executed by issuing one byte command sequence with erase- resume command (30h) at any address in the last byte sequence. when an erase operation is suspended, or re-suspended, after resume the cumulative time neede d for the erase operation to complete is greater than the erase time of a non-suspended erase operation. if the hold time from erase-resume to the next erase- suspend operation is less than 200s, the accu- mulative erase time can become very long therefore, after issuing an erase-resume command, the system must wait at least 200s before issuing another erase-suspend command. the erase-resume command will be ignored until any program operations initiated during erase- suspend are complete. bypass mode can be entered while in erase-suspend, but only bypass word-program is available for those sectors or blocks that are not suspended. bypass sector-erase, bypass block-erase, and bypass chip-erase, erase-suspend, and erase-resume are not available. in order to resume an erase operation, the bypass mode must be exited before issuing erase-resume. for more information about bypass mode, see ?bypass mode? on page 17. chip-erase operation the sst38vf6401/6402/6403/6404 devices provide a chip-erase operation, which erases the entire memory array to the ?1? state. this operation is useful when the entire device must be quickly erased. the chip-erase operation is init iated by executing a six-byte command sequence with chip-erase command (10h) at address 555h in the last byte sequence. the erase operation begins with the rising edge of the sixth we# or ce#, whichever occurs first. during the erase operation, the only valid re ads are toggle bit, data# polling, or ry/by#. see table 11 for the command seq uence, figure 13 for tim- ing diagram, and figure 29 for the flowchart. any commands issued during the chip-erase operation are ignored. if wp# is low, or any vpbs or nvpbs are in the protect state, any attempt to execute a chip-erase operation is ignored. during the command sequence, wp# should be statically held high or low. write operation status detection to optimize the system write cycle time, the sst38vf6401/6402/6403/6404 pro vide two software means to detect the completion of a write (program or erase) cycle the software detection includes two status bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the rising edge of we#, which initiates the internal program or erase operation. the actual completion of the nonvolatile write is asynchronous with the system. therefore, data# poll- ing or toggle bit maybe be read concurrent with the completion of the write cycle. if this occurs, the system may possibly get an incorrect result from the status detection process. for example, valid dat a may appear to conflict with either dq 7 or dq 6 . to prevent false results, upon detection of failures, the software routine should loop to read the accessed location an additional two times. if both reads a re valid, then the device has completed the wr ite cycle, otherwise the failure is valid. for the write-buffer programming feature, dq 1 informs the user if either the write-to-buffer or pro- gram buffer-to-flash operation aborts. if either operation aborts, then dq 1 = 1. dq 1 must be cleared to '0' by issuing the write-to -buffer abort reset command. the sst38vf6401/6402/6403/6404 also provide a ry/by# signal. this signal indicates the status of a program or erase operation. downloaded from: http:///
?2015 ds-20005015b 08/15 13 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs if a program or erase oper ation is attempted on a protected sector or bloc k, the operation will abort. after the device initiate s an abort, the corresponding write op eration status dete ction bits will stay active for approximately 200ns (program or erase) before the device returns to read mode. for the status of these bits during a write operation, see table 4. data# polling (dq 7 ) when the sst38vf6401/6402/6403/6404 are in an internal program operation, any attempt to read dq 7 will produce the complement of tr ue data. for a program buffer-t o-flash operation, dq7 is the complement of the last word loaded in the write-buffer using the write-to-buffer command. once the program operation is completed, dq 7 will produce valid data. note that even though dq 7 may have valid data immediately following the completion of an internal write operation, the remaining data outputs may still be invalid. valid data on the entire data bus will appear in subsequent successive read cycles after an interval of 1 s. during an internal erase operation, any attempt to read dq 7 will produce a ?0?. once the internal erase operation is completed, dq 7 will produce a ?1?. the data# polling is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sect or-, block- or chip-erase, the data# polling is valid after the rising edge of sixth we# (or ce#) pulse. see figure 11 for data# polling timing diagram and figure 26 for a flowchart. toggle bits (dq 6 and dq 2 ) during the internal program or erase operation, any consecutive attempts to read dq 6 will produce alternating ?1?s and ?0?s, i.e., toggling between ?1? and ?0?. when the internal program or erase opera- tion is completed, the dq 6 bit will stop toggling, and the device is then ready fo r the next operation. for sector-, block-, or chip-erase, the toggle bit (dq 6 ) is valid after the rising edge of sixth we# (or ce#) pulse. dq 6 will be set to ?1? if a read operation is atte mpted on an erase-susp ended sector or block. if program operation is initiated in a sector/block not selected in erase-suspend mode, dq 6 will toggle. an additional toggle bit is available on dq 2 , which can be used in conjunction with dq 6 to check whether a particular sector or block is being ac tively erased or erase-suspended. table 4 shows detailed bit status information. the toggle bit (dq 2 ) is valid after the rising edge of the last we# (or ce#) pulse of write operation. see figure 12 for toggle bit timing diagram and figure 26 for a flo w- chart. dq 1 if an operation aborts during a write-to-buffer or program buffer-to-flash operation, dq 1 is set to ?1?. to r e s e t d q 1 to ?0?, issue the write-to-buffer abort reset command to exit the abort state. a power-off/ power-on cycle or a hardware re set (rst# = 0) will also clear dq 1 . downloaded from: http:///
?2015 ds-20005015b 08/15 14 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs ry/by# the ry/by# pin can be used to determine the status of a program or erase operation. the ry/by# pin is valid after the rising edge of the final we# pulse in the command sequence. if ry/by# = 0, then the device is actively programming or erasing. if ry/by# = 1, the device is in read mode. the ry/by# pin is an open drain output pin. this means several ry/by# can be tied together with a pull-up resistor to v dd.. data protection the sst38vf6401/6402/6403/6404 provide both hardware and software feat ures to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection: a we# or ce# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhibited when v dd is less than 1.5v. write inhibit mode: forcing oe# low, ce# high, or we# high will inhibit the write operation. this pre- vents inadvertent writes during power-up or power-down. table 4: write operation status status dq 7 1 1. dq 7 and dq 2 require a valid address when reading status information. dq 6 dq 2 1 dq 1 ry/by# 2 2. ry/by# is an open drain pin. ry/by# is high in read mode, and read in erase-suspend mode. normal operation standard program dq 7 # toggle no toggle 0 0 standard erase 0 toggle toggle n/a 0 erase-suspend mode read from erase-suspended sector/block 1 no toggle toggle n/a 1 read from non- erase- suspended sector/block data data data data 1 program dq 7 # toggle n/a n/a 0 program buffer-to-flash busy dq 7 # 3 3. during a program buffer-to-flash operation, the datum on the dq 7 pin is the complement of dq 7 of the last word loaded in the write-buffer using the write-to-buffer command. toggle n/a 0 0 abort dq 7 # 3 toggle n/a 1 0 t4.0 20005015 downloaded from: http:///
?2015 ds-20005015b 08/15 15 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs hardware block protection the sst38vf6402 and sst39vf6404 devices support top hardware block protection, which protects the top boot block of the device. for sst38vf6402, the boot block consists of the top 32 kword block, and for sst39vf6404 the boot block consists of the top two 4 kword sectors (8 kword total). the sst38vf6401 and sst38vf6403 devices support bottom hardware block protection, which pro- tects the bottom boot block of the device. for sst38vf6401, the boot block consists of the bottom 32 kword block, and for sst39vf6403 the boot block consists of the bottom two 4 kword sectors (8 kword total). the boot block addresses are described in table 5. program and erase operations are prevented on the boot block when wp# is low. if wp# is left float- ing, it is internally held high via a pull-up resistor. when wp# is high, the boot block is unprotected, which allows program and erase operations on that area. hardware reset (rst#) the rst# pin provides a hardware method of resetting the device to read array data. when t he rst# pin is held low for at least t rp, any in-progress operation will termin ate and return to read mode. when no internal program/erase operation is in progress, a minimum period of t rhr is required after rst# is driven high before a valid read can take place. see figure 20 for more information. the interrupted erase or program operation must be re-initiated after the device resumes normal oper- ation mode to ensure data integrity. software data protection (sdp) the sst38vf6401/6402/6403/6404 devices implement the jedec approved softwar e data protection (sdp) scheme for all data alteration operations, such as program and erase. these devices are shipped with the software data protection permanently enabled. see table 11 for the specific software command codes. all program operations require the inclusion of the three-byte sequence. the three-byte load sequence is used to initiate the program operation, providing optimal protection from inadvertent write opera- tions. sdp for erase operations is similar to program, but a six-byte load sequence is required for erase operations. during sdp command sequence, in valid commands will abort the devi ce to read mode within t rc. the contents of dq 15 -dq 8 can be v il or v ih , but no other value, during any sdp command sequence. table 5: boot block address ranges product size address range bottom boot uniform sst38vf6401 32 kw 000000h-007fffh top boot uniform sst38vf6402 32 kw 3f8000h-3fffffh bottom boot non-uniform sst38vf6403 8 kw 000000h-001fffh top boot non-uniform sst38vf6404 8 kw 3fe000h-3fffffh t5.0 20005015 downloaded from: http:///
?2015 ds-20005015b 08/15 16 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs the sst38vf6401/6402/6403/6404 devices provide bypass mode, which allows for reduced program and erase command sequence lengths. in this mode, the sdp portion of program and erase com- mand sequences are omitted. see ?bypass mode? on page 17. for further details. common flash memory interface (cfi) the sst38vf6401/6402/6403/6404 contain common flash memory interface (c fi) information that describes the characteristics of the device. in order to enter the cfi query mode, the system can either write a one-byte sequence using a standard cfi query entry command, or a three-bye sequence using the sst cfi query entry command. a comparison of these two commands is shown in table 11. once the device enters the cfi query mode, the system can read cfi data at the addresses given in tables 13 through 16. the system must write the cfi exit command to return to read mode. note that the cfi exit com- mand is ignored during an internal program or erase operation. see table 11 for software command codes, figures 17 and 18 for timing waveform, and figures 27 and 28 for flowcharts. product identification the product identification mode identifies the devices as the sst38vf6401, sst38vf6402, sst38vf6403, or sst38vf6404, and the manufacturer as sst. see table 6 for specific address and data information. product identification mode is accessed through software operations. the software product identification operations identify the part, and can be useful when using multiple manufactur- ers in the same socket. for details, see table 11 for software operation, figure 16 for the softwar e id entry and read timing diagram, and figure 27 for the software id entry command sequence flowchart. while in product identification mode, the read block protection status command determines if a block is protected. the status returned indicates if the block has been protected, but does not differentiate between volatile block protection and non-volatile block protection. see table 11 for further details. the read-irreversible block-lock status command indicates if the irreversible block command has been issued. if dq 0 = 0, then the irreversible lock command has been previously issued. in order to return to the standard read mode, the software product identification mode must be exited. the exit is accomplished by issuing the software id exit command sequence, which return s the device to the read mode. see table 11 for software command codes, figure 18 for timing waveform, and fi g- ures 27 and 28 for flowcharts. table 6: product identification address data manufacturer?s id 0000h bfh device id sst38vf6401 0001h 536b sst38vf6402 0001h 536a sst38vf6403 0001h 536d sst38vf6404 0001h 536c t6.0 20005015 downloaded from: http:///
?2015 ds-20005015b 08/15 17 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs security id the sst38vf6401/6402/6403/6404 devices offer a security id feature. the secu re id space is divided into two segments ? one factory programmed 128 bit segment and one user programmable 256 word segment. see table 7 for address information. the first segment is programmed and locked and con- tains a 128 bit unique id which uniquely identifies the device. the user segment is left un-programmed for the customer to program as desired. the user segment of the security id can be programmed in several ways. for smaller datasets, use the security id word-program command for word-programming. to program larger sets of data mo re quickly, use the sec id entry command to enter the secure id space. once in the secure id space, use the write-buffer programming or bypass mode feature. note that the word-programming com- mand can also be used while in this mode. to detect end-of-write for the sec id, read the toggle bits. do not use data# polling to detect end of write. once the programming is complete, lock the sec id by issuing the user sec id program lo ck- out command or by programming bit ?0? in the psr with the psr program command. locking the sec id disables any corruption of this space. note that regardless of whether or not the sec id is locked, the sec id segments can not be erased. the secure id space can be queried by executing a three-byte command sequence with enter sec id command (88h) at address 555h in the last byte sequence. to exit this mode, the exit sec id com- mand should be executed. refer to table 11 for software commands and figures 27 and 28 for f low charts. bypass mode bypass mode shortens the time needed to issue program and erase commands by reducing these commands to two write cycles each. after using the bypass entry command to enter the bypass mode, only the bypass word-program, bypass sector erase, bypass block erase, bypass chip erase, erase-suspend, and erase-resume commands are available. the bypass exit command exits bypass mode. see table 11 for further details. entering bypass mode while already in erase-suspend limits the available commands. see ?erase- suspend/erase-resume commands? on page 11. for more information. table 7: address range for sec id size address unique id 128 bits 000h ? 007h user 256 w 100h ? 1ffh t7.1 20005015 downloaded from: http:///
?2015 ds-20005015b 08/15 18 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs protection settings register (psr) the protection settings register (psr) is a user-programmable register that allows for further custom- ization of the sst38vf6401/6402/6403/6404 protection features. the 16-bit psr provides four one time programmable (otp) bits for users, each of which can be programmed individually. howe ver, once an otp bit is programmed to ?0?, the value cannot be changed back to a ?1?. the other 12 bits of the psr are reserved. see table 8 for the definition of all 16-bits of the psr. note that dq 4 , dq 2 , dq 1 , dq 0 do not have to be programmed at the same time. in addition, dq2 and dq1 cannot both be programmed to ?0?. the valid combinations of states of dq 2 and dq 1 are shown in table 9. the psr can be accessed by issuing the psr entry command. users can then use the psr program and psr read commands. the psr exit command must be issued to leave this mode. see table 11 for further details. table 8: psr bit definitions bit default from factory definition dq 15 -dq 5 fffh reserved dq 4 1 vpb power-up / hardware reset state 0 = all protected 1 = all unprotected dq 3 1 reserved dq 2 1 password mode 0 = password only mode 1 = pass-through mode dq 1 1 pass-through mode 0 = pass-through only mode 1 = pass-through mode dq 0 1 sec id lock out bit 0 = locked 1 = unlocked t8.0 20005015 table 9: valid dq 2 and dq 1 combinations combination definition dq 2 , dq 1 = 11 pass-through mode (factory default) dq 2, dq 1 = 10 pass-through only mode dq 2 , dq 1 = 01 password only mode dq 2 , dq 1 = 00 not allowed t9.0 20005015 downloaded from: http:///
?2015 ds-20005015b 08/15 19 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs individual block protection the sst38vf6401/6402/6403/6404 provide two methods for individual block protection: volatile block protection and non-volatile block protection. data in protected blocks cannot be altered. volatile block protection the volatile block protection feature provides a faster method than non-volatile protection to prot ect and unprotect 32 kword blocks. each block has it ?s own volatile protec tion bit (vpb). in the sst38vf6401/2, the 32 kword boot block also has a vpb. in the sst38vf6403/4 devices, each of the two 4 kword sectors in the 8 kword boot area has it's own vpb. after using the volatile block protection mode entry command to enter the volatile block protection mode, individual vpbs can be set or reset with vpb set/clear, or be read with vpb status read. if the vpb is ?0?, then the block is protected from program and erase. if the vpb is ?1?, then the block is unprotected. the volatile block protection exit command must be issued to exit volatile block protec- tion mode. see table 11 for further details on the commands and figure 31 for a flow chart. if the device experiences a hardware reset or a power cycle, all the vpbs return to their default state as determined by user-programmable bit dq 4 in the psr. if dq 4 is ?0?, then all vpbs default to ?0? (pro- tected). if dq 4 is ?1?, then all vpbs def ault to ?1? (unprotected). non-volatile block protection the non-volatile block protection feature provides protection to individual blocks using non-volatile protection bits (nvpbs). each bloc k has it?s own non-volatile protec tion bit. in the sst38vf6401/2, the 32 kword boot block also has a it's own nvpb. in the sst38vf6403/4, each 4 kword sector in the 8kword boot area has it's own nvpb. all nvpbs come from the factory set to ?1?, the unprotected state. use the non-volatile block protection mode entry command to enter the non-volatile block protection mode. once in this mode, the nvpb program command can be used to protect individual blocks by setting individual nvpbs to ?0?. the time needed to prog ram an nvpb is two times t bp, which is a max- imum of 20s. the nvpb status r ead command can be used to check the protecti on state of an indi- vidual nvpb. to change an nvpb to ?1?, the unp rotected state, the nvpb must be erased using nvpbs erase com- mand. this command erases all n vpbs to ?1?. nvpb program should be used to set the nvpbs of any blocks that are to be protected before exiting the non-volatile block protection mode. see ta ble 11 and figure 32 for further details. upon a power cycle or hardware reset, the nvpbs retain their states. memory areas that ar e protected using non-volatile block protection remain pr otected. the nvpb program and nvpbs erase com- mands are permanently disabled once the irreversible block lock command is issued. see ?irrevers- ible block locking? on page 22 for further information. downloaded from: http:///
?2015 ds-20005015b 08/15 20 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs advanced protection the sst38vf6401/6402/6403/6404 provide advanced protection features that allow users to imple- ment conditional access to the nvpbs. specifically , advanced protection uses the global lock bit to protect the nvpbs. if the global lock bit is ?0? then all the nvpbs states are froz en and cannot be modified in any mode. if the global lock bit is ?1?, then all the nvpbs can be modified in non-volatile block protection mode. after using the global lock of nvpbs entry command to enter the global lock of nvpbs mode, the global lock bit can be acti vated by issuing a set global lock bit command, which sets the global lock bit to ?0?. the global lock bit cannot be set to ?1? with this command. the status of the bit can be read with the global lo ck bit status command. us e the global lock of nvpbs exit command to exit global loc k of nvpbs mode. see table 11 an d figure 33 for further details. the steps used to change the glo bal lock bit from '0' to'1,' to allow access to the nvpbs, depend on whether the device has been set to use pass-through or password mode. when using advanced pro- tection, select either pass-through only mode or password only mode by programming the dq 2 and dq 1 bits in the psr. although the factory default is pass-through mode (dq 2 = 1, dq 1 = 1), the user should explicitly chose either pass-through only mode (dq 2 = 1, dq 1 = 0), or password only mode (dq 2 = 0, dq 1 = 1). keeping the sst38vf6401/6402/6403/6404 in the factory default pass-through mode leaves the device open to unauthorized changes of dq 2 and dq 1 in the psr. see ?protection settings register (psr)? on page 18. for more information about the psr. pass-through mode (dq 2 , dq 1 = 1,0) the pass-through mode allows the global lock bit state to be cleared to ?1? by a power-down power- up sequence or a hardware reset (rst# pin = 0). no password is required in pass-through mode. to set the global lock bit to ?0?, use the set global lock bit command while in the global lock of nvpbs mode. select the pass-through only mode by programming psr bit dq 2 = 1 and dq 1 = 0. password mode (dq 2 , dq 1 = 0,1) in the password mode, the global lock bit is set to ?0? by the set global lock bit command, a power- down power-up sequence, or a hardware reset (rst# pin = 0). select the password only mode by pro- gramming psr bit dq 2 = 0 and dq 1 = 1. note that when the psr program command is issued in password mode, the global lock bit is automatically set to ?0?. in contrast to the pass-through mode, in the password mode, the only way to clear the gl obal lock bit to ?1? is to submit the correct 64-bit password using the submit password command in password com- mands mode. the words of the password can be submitted in any order as long as each 16 bit section of the password is matched with its correct address. after the entire 64 bit password is submitted, the device takes approximately 2 s to verify the password. a subsequent submit password command cannot be issued until this verification time has elapsed. the 64-bit password must be chosen by the user before programming the dq 2 and dq 1 otp bits of the psr to choose password mode. the default 64 bit password on the device from the factory is ffffffffffffffffh. enter the password commands mode by issuing the password commands entry command. then, use the password program command to program the desired password. use caution when program- ming the password because there is no method to reset the password to ffffffffffffffffh. once a password bit has been set to ?0?, it cannot be changed back to ?1?. see table 11 for further details about password-related commands. downloaded from: http:///
?2015 ds-20005015b 08/15 21 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs the password can be read using the password read command to verify the desired password has been programmed. microchip recommends testing the password before permanently choosing pass- word mode. to test the password, do the following: 1. enter the global lock of nvpbs mode. 2. set the global lock bit to ?0?, and verify the value. 3. exit the global lock of nvpbs mode. 4. enter the password commands mode. 5. submit the 64-bit password with the submit password command. 6. wait 2 s for the device to verify the password. 7. exit the password commands mode. 8. re-enter the global lock of nvpbs mode 9. read the global lock bit with the global lock bit status read command. the global lock bit should now be ?1?. after verifying the password, program the dq 2 and dq 1 otp bits of the psr to explicitly choose pass- word mode. once the password mode has been selected, the password read and password program commands are permanently disabled. there is no longer any method for reading or modifying the password. in addition, microchip is unable to read or modify the password. if a password read com- mand is issued while in password mode, the data presented for each word of the password is ffffh. if the password mode is not exp licitly chosen in the psr, then th e password can still be read and mod- ified. therefore, microchip strongly recommends that users explicitly choose password mode in the psr. downloaded from: http:///
?2015 ds-20005015b 08/15 22 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs irreversible block locking the sst38vf6401/6402/6403/6404 provides irreversible block locking, a feature that allows users to customize the size of read-only me mory (rom) on the device and pr ovides more flexibility than one- time programmable (otp) memory. applying irreversible block locking turns user-sel ected memory areas into rom by permanently dis- abling program and erase operations to these chosen areas. any area that becomes rom cannot be changed back to flash. any memory blocks in the main memory, including bo ot blocks, can be irreversibly locked. in non-uni- form boot block devices (sst38vf6403 and sst38vf6404) each 4 kw sector in the boot area can be irreversibly locked. if desired, all blocks in the main memory can be irreversibly locked. to use irreversible block locking do the following: 1. global lock bit should be ?1?. the irreversible block lock command is disabled when global lock bit is ?0?. 2. enter the non-volatile block protection mode. 3. use the nvpb program command to protect only the blocks that ar e to be changed into rom. 4. exit the non-volatile block protection mode. 5. issue the irreversible block lock command (see table 11 for details). the irreversible block lock command can only be used once. issuing the command after the first time has no effect on the device. important: once the irreversible block lock command is used, the state of the nvpbs can no longer be changed or overridden. therefore, the following features no longer have any effect on th e device: ? global lock of nvpbs feature ? password feature ? nvpb program command ? nvpb erase command ? dq2 and dq1 of psr in addition, wp# has no effect on any memory in the boot block area that has been irreversibly locked. to verify whether the irreversible block lock command has already been issued, enter th e product id mode and read address 5feh. if dq 0 = 0, then irreversible block lock has already been executed. when using this feature to dete rmine if a specific block is rom, use the nvpb status read. downloaded from: http:///
?2015 ds-20005015b 08/15 23 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs operations table 10: operation modes selection mode ce# oe# we# rst# wp# dq address read v il v il v ih hxd out a in program v il v ih v il hv il /v ih 1 1. wp# can be v il when programming or erasing outside of the bootblock. wp# must be v ih when programming or erasing inside the bootblock area. d in a in erase v il v ih v il hv il /v ih 1 x 2 2. x can be v il or v ih , but no other value. sector or block address, xxh for chip-erase standby v ih xxv ih x high z x write inhibit x v il x x x high z/ d out x product identification x x v ih h x high z/ d out x reset x x x l x high z x software mode v il v ih v il h x see table 11 see table 11 t10.0 20005015 downloaded from: http:///
?2015 ds-20005015b 08/15 24 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs table 11: software command sequence (1 of 3) command sequence 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle 7th bus cycle addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 read 3 wa data page read 3 wa 0 data 0 wa 1 data 1 wa 2 data 2 wa 3 data 3 word-program 555h aah 2aah 55h 555h a0h wa data write-buffer programming write-to-buffer 4 555h aah 2aah 55h ba 25h ba wc wa x data wa x data wa x data program buffer- to- flash ba x 29h write-to-buffer abort-reset 555h aah 2aah 55h 555h f0h bypass mode 5 bypass mode entry 555h aah 2aah 55h 555h 20h bypass word-pro- gram xxxh a0h wa data bypass sector erase xxxh 80h sa 50h bypass block erase xxxh 80h ba 30h bypass chip erase xxxh 80h 555h 10h bypass mode exit xxxh 90h xxxh 00h erase related sector-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa x 50h block-erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h bax 30h chip-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h erase suspend xxxh b0h erase resume xxxh 30h security id sec id entry 7 555h aah 2aah 55h 555h 88h sec id read 3, 8 wa x data sec id exit 555h aah 2aah 55h 555h 90h xxh 00h software id exit /cfi exit/sec id exit 9 555h aah 2aah 55h 555h f0h software id exit /cfi exit/sec id exit 9 xxh f0h user security id word-pro- gram 10 555h aah 2aah 55h 555h a5h wa x data user security id program lock- out 555h aah 2aah 55h 555h 85h xxh 0000h downloaded from: http:///
?2015 ds-20005015b 08/15 25 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs product identification software id entry 11 555h aah 2aah 55h 555h 90h manufacturer id 3, 12 x00 bfh device id 3, 12 x01 data read block protection sta- tus 3 bax02 13 data 14 read irrevers- ible block lock status 3 5feh data 15 read global lock bit sta- tus 3 9ffh data 16 software id exit /cfi exit/sec id exit 9 555h aah 2aah 55h 555h f0h software id exit /cfi exit/sec id exit 9 xxh f0h volatile block protection volatile block protection mode entry 555h aah 2aah 55h 555h e0h volatile protec- tion bit (vpb) set/clear xxh a0h ba x 17 data 18 vpb status read 3 ba x data 18 volatile block protection mode exit xxh 90h xxh 00h non-volatile block protection non-volatile block protection mode entry 555h aah 2aah 55h 555h c0h non-volatile protect bit (nvpb) program xxh a0h ba x 17 00h non-volatile protect bits (nvpb) erase 19 xxh 80h 00h 30h nvpb status read 3 ba x 17 data 18 non-volatile block protection mode exit xxh 90h xxh 00h table 11: software command sequence (continued) (2 of 3) command sequence 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle 7th bus cycle addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 downloaded from: http:///
?2015 ds-20005015b 08/15 26 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs global lock of nvpbs global lock of nvpbs entry 555h aah 2aah 55h 555h 50h set global lock bit xxh a0h xxh 00h global lock bit status read 3 xxxh data 16 global lock of nvpbs exit xxh 90h xxh 00h password commands password com- mands mode entry 555h aah 2aah 55h 555h 60h password pro- gram 20 xxh a0h pwa x pwdx password read 3 pwa x pwd x submit pass- word 21 00h 25h 00h 03h 00h pwd 0 01h pwd 1 02h pwd 2 03h pwd 3 00h 29h password com- mands mode exit xxh 90h xxh 00h program and settings register (psr) psr entry 555h aah 2aah 55h 555h 40h psr program 22 xxh a0h xxxh data psr read 3 xxh data psr exit xxh 90h xxh 00h cfi cfi query entry 23 55h 98h sst cfi query entry 23 555h aah 2aah 55h 555h 98h software id exit /cfi exit/sec id exit 9 555h aah 2aah 55h 555h f0h software id exit/cfi exit/ sec id exit 9 xxh f0h irreversible block lock irreversible block lock 24 555h aah 2aah 55h 555h 87h xxh 00h t11.0 20005015 1. address format a 10 -a 0 (hex). addresses a 11 - a 21 can be v il or v ih, but no other value, for the sst38vf6401/6402/ 6403/6404 command sequence. 2. dq 15 -dq 8 can be v il or v ih , but no other value, for command sequence 3. all read commands are in bold italics . table 11: software command sequence (continued) (3 of 3) command sequence 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle 7th bus cycle addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 downloaded from: http:///
?2015 ds-20005015b 08/15 27 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs note: table 11 uses the following abbreviations: x = don?t care (v il or v ih , but no other value. sa x = sector address; uses a ms -a 12 address lines ba x = block address; uses a ms -a 15 address lines wa = word address wc = word count pwa x = password address; pwa x = pwa 0 , pwa 1 , pwa 2 or pwa 3; a1 and a0 are used to select each 16-bit portion of the password pwd x = password data; pwd x = pswd 0 , pwd 1 , pwd 2 , or pwd 3 a ms = most significant address 4. total number of cycles in this command sequence depends on the number of words to be written to the buffer. additional words are written by repeating write cycle 5. address (wa x ) values for write cycle 6 and later must have the same a21-a4 values as wa x in write cycle 5. wc = word count. the value of wc is the number of words to be written into the buffer, minus 1. maximum wc value is 15 (i.e. f hex) 5. erase-suspend and erase-resume commands are also available in bypass mode. 6. for sst39vf6403, sector-erase or block-erase can be us ed to erase sectors s1016 - s1023. use address sax. block erase cannot be used to erase all 32kw of block b127. for sst39vf6404, sector-erase or block-erase can be used to erase sectors s0 - s7. use address sax. block eras e cannot be used to erase all 32kw of block b0. 7. once in sec id mode, the word-program, write-buffer programming, and bypass word-program features can be used to program the sec id area. 8. unique id is read with a 3 = 0 (address range = 000000h to 000007h), user portion of sec id is read with a 8 = 1 (address range = 000100h to 0001ffh). lock-out status is read with a 7 -a 0 = ffh. unlocked: dq 3 = 1 / locked: dq 3 = 0. lock status can also be checked by reading bit ?0? in the psr. 9. both software id exit operations are equivalent 10. if bits are not locked, then the user-programmable portion of the sec id can be programmed over the previously unpro- grammed bits (data =1) using the sec id mode again (bits programmed ?0? cannot be reversed to ?1?). valid word- addresses for the user-programmable portion of the sec id are from 000100h-0001ffh. 11. the device does not remain in software product id mode if powered down. 12. with a ms -a 1 =0; manufacturer id = 00bfh, is read with a 0 = 0, sst38vf6401 device id = 536b, is read with a 0 = 1, sst38vf6402 device id = 536a, is read with a 0 = 1, sst38vf6403 device id = 536d, is ready with a 0 = 1, sst38vf6404 device id = 536c, is read with a 0 = 1. 13. ba x02 : a ms -a 15 = block address; a 14 -a 8 = xxxxxx; a 7 -a 0 = 02 14. data = 00h unprotected block; data = 01h protected block. 15. dq 0 = 0 means the irreversible block lock command has been previously used. dq 0 = 1 means the irreversible block lock command has not yet been used. 16. dq 0 = 0 means that the global lock bit is locked. dq 0 = 1 means that the global lock bit is unlocked. 17. for non-uniform boot block devices (i.e. 8 kword size), in the boot area, use sa x = sector address (sector size = 4 kword). 18. dq 0 = 0 means protected; dq 0 = 1 means unprotected 19. erases all nvpbs to ?1? (unprotected) 20. entire two-bus cycle sequence must be ent ered for each portion of the password. 21. entire password sequence required for va lidation. the word order doesn?t matter as long as the address and data pair match. 22. reserved register bits (dq 15 -dq 5 and dq 3 ) must be ?1? during program. 23. cfi query entry and sst cfi query entry are equivale nt. both allow access to the same cfi tables. 24. global lock bit must be ?1? before executing this command. downloaded from: http:///
?2015 ds-20005015b 08/15 28 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs table 12: protection priority for main array nvpb 1 vpb 1 protection state of block protect x protected x protect protected unprotect unprotect unprotected t12.0 20005015 1. x = protect or unprotect table 13: cfi query identification string 1 for sst38vf6401/6402/6403/6404 1. refer to cfi publication 100 for more details. address data description 10h 0051h query unique ascii string ?qry? 11h 0052h 12h 0059h 13h 0002h primary oem command set 14h 0000h 15h 0040h address for primary extended table 16h 0000h 17h 0000h alternate oem command set (00h = none exists) 18h 0000h 19h 0000h address for alternate oem extended table (00h = none exits) 1ah 0000h t13.0 20005015 downloaded from: http:///
?2015 ds-20005015b 08/15 29 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs table 14: system interface information for sst38vf6401/6402/6403/6404 address data description 1bh 0027h v dd min (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1ch 0036h v dd max (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1dh 0000h v pp min. (00h = no v pp pin) 1eh 0000h v pp max. (00h = no v pp pin) 1fh 0003h typical time out for word-program 2 n s (2 3 = 8 s) 20h 0003h typical time out for min. size buffer program 2 n s (00h = not supported) 21h 0004h typical time out for individual sector/block-erase 2 n ms (2 4 = 16 ms) 22h 0005h typical time out for chip-erase 2 n ms (2 5 = 32 ms) 23h 0001h maximum time out for word-program 2 n times typical (2 1 x 2 3 = 16 s) 24h 0003h maximum time out for buffer program 2 n times typical 25h 0001h maximum time out for individual sector/block-erase 2 n times typical (2 1 x 2 4 = 32 ms) 26h 0001h maximum time out for chip-erase 2 n times typical (2 1 x 2 5 = 64 ms) t14.0 20005015 table 15: device geometry information for sst38vf6401/6402/6403/6404 address data description 27h 0017h device size = 2 n bytes (17h = 23; 2 23 = 8 mbyte) 28h 0001h flash device interface description; 0001h = x16-only asynchronous interface 29h 0000h 2ah 0005h maximum number of bytes in multi-byte write = 2 n (00h = not supported) 2bh 0000h 2ch 0002h number of erase sector/block sizes supported by device 2dh 00ffh sector information (y + 1 = number of sectors; z x 2 56b = sector size) 2eh 0003h y = 2047 + 1 = 2048 sectors (03ffh = 1023) 2fh 0000h 30h 0001h z = 32 x 256 bytes = 8 kbytes/sector (0100h = 32) 31h 007fh block information (y + 1 = number of blocks; z x 256b = block size) 32h 0000h y =127 + 1 = 128 blocks (007fh = 127) 33h 0000h 34h 0001h z = 256 x 256 bytes = 64 kbytes/block (0100h = 256) t15.1 20005015 downloaded from: http:///
?2015 ds-20005015b 08/15 30 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs table 16: primary vendor-specific extended information for sst38vf6401/6402/6403/ 6404 address data description 40h 0050h 41h 0052h query-unique ascii string ?pri? 42h 0049h 43h ffffh reserved 44h ffffh reserved 45h 0000h reserved 46h 0002h erase suspend 0 = not supported, 1 = only read during erase suspend, 2 = read and program during erase suspend. 47h 0001h individual block protection 0 = not supported, 1 = supported 48h 0000h reserved 49h 0008h protection 0008h = advanced 4ah 0000h simultaneous operation 00 = not supported 4bh 0000h burst mode 00 = not supported 4ch 0001h page mode 00 = not supported, 01 = 4 word page. 4dh 0000h acceleration supply minimum 00 = not supported 4eh 0000h acceleration supply maximum 00 = not supported 4fh 00xxh top / bottom boot block 02h = 8 kword bottom boot 03h = 8 kword top boot 04h = uniform (32 kword) bottom boot 05h = uniform (32 kword) top boot 50h 0000h program suspend 00h = not supported, 01h = supported t16.1 20005015 downloaded from: http:///
?2015 ds-20005015b 08/15 31 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs absolute maximum stress ratings (applied conditions greater than those listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating con- ditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 c to +12 5c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 c to + 150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . -2 .0v to v dd +2.0v voltage on a 9 pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 12.5v voltage on rst# pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 1 2.5v voltage on wp# pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 1 2.5v package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount solder reflow temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds output short circuit current 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. outputs shorted for no more than one second. no more than one output shorted at a time. table 17: operating range range ambient temp v dd commercial 0c to +70c 2.7-3.6v industrial -40c to +85c 2.7-3.6v t17.1 20005015 table 18: ac conditions of test 1 1. see figures 22 and 23 input rise/fall time output load 5ns c l = 30 pf t18.1 20005015 downloaded from: http:///
?2015 ds-20005015b 08/15 32 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs power-up specifications all functionalities and dc specif ications are specified for a v dd ramp rate faster than 1v per 100 ms (0v to 3v in less than 300 ms). if the v dd ramp rate is slower than 1v per 100 ms, a hardware reset is required. the recommended v dd power-up to reset# high time sh ould be greater than 100 s to ensure a proper reset. see table 19and figure 4 for more information. figure 4: power-up diagram table 19: recommended system power-up timings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for initial qualification and after a desig n or process change that could affect this parameter. power-up to read operation 100 s t pu-write 1 power-up to erase/program operation 100 s t19.0 20005015 1309 f37.0 v dd reset# ce# t pu-read > 100 s v dd min 0v v ih t rhr > 50ns downloaded from: http:///
?2015 ds-20005015b 08/15 33 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs dc characteristics table 20: dc operating characteristics v dd = 2.7-3.6v 1 1. typical conditions for the active current shown on the front page of the data sheet are average values at 25c (room temperature), and v dd = 3v. not 100% tested. symbol parameter limits test conditions min max units i dd power supply current address input=v ilt /v iht 2 , v dd =v dd max 2. see figure 27 read 3 3. the i dd current listed is typically less than 2ma/mhz, with oe# at v ih. ty p i c a l v dd is 3v. 18 ma ce#=v il , oe#=we#=v ih at f= 5 mhz intra-page read @5 mhz 2.5 ma ce#=v il , oe#=we#=v ih intra-page read @40 mhz 20 ma ce#=v il , oe#=we#=v ih program and erase 35 ma ce#=we#=v il , oe#=v ih program-write-buffer-to- flash 50 ma ce#=we#=v il , oe#=v ih i sb standby v dd current 30 a ce#=v ihc , v dd =v dd max i alp auto low power 20 a ce#=v ilc , v dd =v dd max all inputs=v ss or v dd, we#=v ihc i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i liw input leakage current on wp# pin and rst# 10 a wp#=gnd to v dd or rst#=gnd to v dd i lo output leakage current 10 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ilc input low voltage (cmos) 0.3 v v dd =v dd max v ih input high voltage 0.7v dd vv dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v v dd =v dd max v ol output low voltage 0.2 v i ol =100 a, v dd =v dd min v oh output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min t20.0 20005015 table 21: capacitance (t a = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for initial qualification and after a desig n or process change that could affect this parameter. i/o pin capacitance v i/o = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf t21.0 20005015 table 22: reliability characteristics symbol parameter minimum specification units test method n end 1,2 1. this parameter is measured only for initial qualification and after a desig n or process change that could affect this parameter. 2. n end endurance rating is qualified as 100,000 cycles minimum per block. endurance 100,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t22.0 20005015 downloaded from: http:///
?2015 ds-20005015b 08/15 34 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs ac characteristics table 23: read cycle timing parameters v dd = 2.7-3.6v symbol parameter min max units t rc read cycle time 90 ns t ce chip enable access time 90 ns t aa address access time 90 ns t pac c page access time 25 ns t oe output enable access time 25 ns t clz 1 1. this parameter is measured only for initial qualification and after a desig n or process change that could affect this parameter. ce# low to active output 0 ns t olz 1 oe# low to active output 0 ns t chz 1 ce# high to high-z output 20 ns t ohz 1 oe# high to high-z output 20 ns t oh 1 output hold from address change 0 ns t rp 1 rst# pulse width 500 ns t rhr 1 rst# high before read 50 ns t rye 1,2 2. this parameter applies to sector-erase, block-erase, and program operations. this parameter does not apply to chip-erase operations. rst# pin low to read mode 20 s t ry 1 rst# pin low to read mode ? not during program or erase algorithms. 500 ns t rpd 1 rst# input low to standby mode 20 s t rb 1 ry / by# output high to ce# / oe# pin low 0 ns t23.0 20005015 downloaded from: http:///
?2015 ds-20005015b 08/15 35 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs table 24: program/erase cycle timing parameters symbol parameter min max units t bp word-program time 10 s t wbp 1 program buffer-to-flash time 40 s t as address setup time 0 ns t ah address hold time 30 ns t cs we# and ce# setup time 0 ns t ch we# and ce# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp ce# pulse width 40 ns t wp we# pulse width 40 ns t wph 2 we# pulse width high 30 ns t cph 2 ce# pulse width high 30 ns t ds data setup time 30 ns t dh 2 data hold time 0 ns t ida 2 software id, volatile protect, non-vo latile protect, global lock bit, password mode, lock bit, bypass entry, and exit times 150 ns t se sector-erase 25 ms t be block-erase 25 ms t sce chip-erase 50 ms t busy ce# high or we# high to ry / by# low 90 ns t24.0 20005015 1. effective programming time is 2.5 s per word if 16-words are programmed during this operation. 2. this parameter is measured only for initial qualification and after a desig n or process change that could affect this parameter. downloaded from: http:///
?2015 ds-20005015b 08/15 36 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs figure 5: read cycle timing diagram figure 6: page read timing diagram 1309 f03.1 address a ms-0 dq 15-0 we# oe# ce# data va l i d data va l i d ry/by# high-z v ih high-z t chz t ohz t olz t clz t oh t oe t ce t rc t aa t rb note: a ms = most significant address address a ms-2 a 1 - a 0 dq 15-0 ce# oe# ax ax ax data v alid same page ry/by# data v alid data v alid ax t aa t pac c t pac c t pac c 1309 f24.3 data v alid note: a ms = most significant address a ms = a 21 for sst38vf6401/6402/6403/6404 downloaded from: http:///
?2015 ds-20005015b 08/15 37 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs figure 7: we# controlled program cycle timing diagram t dh t wph t ds t wp t ah t as t ch t cs t busy 1309 f04.1 address a ms-0 dq 15-0 ce# sw0 sw1 sw2 555 2aa 555 addr xxaa xx55 xxa0 data internal program operation starts word (addr/data) oe# we# t bp ry/by# note: a ms = most significant address a ms = a 21 for sst38vf6401/6402/6403/6404 wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value. downloaded from: http:///
?2015 ds-20005015b 08/15 38 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs figure 8: ce# controlled program cycle timing diagram t dh t cph t ds t cp t ah t as t ch t cs t busy 1309 f05.1 address a ms-0 dq 15-0 we# sw0 sw1 sw2 555 2aa 555 addr xxaa xx55 xxa0 data internal program operation starts word (addr/data) oe# ce# t bp ry/by# note: a ms = most significant address a ms = a 21 for sst38vf6401/6402/6403/6404 wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. downloaded from: http:///
?2015 ds-20005015b 08/15 39 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs figure 9: we# controlled write-buffer cycle timing diagram figure 10: we# controlled program-write-buffer-to-flash cycle timing diagram 1309 f34.2 address a ms-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 swn 555 2aa wa x ba ba data data n xx55 xxaa xx25 wc wa x oe# ce# ry/by# fill write buffer with data t wp note: ba= block address wa x = word address wc = word count datan = nth data 1309 f35.1 address a ms-0 dq 15-0 we# ba 29h oe# ce# t busy ry/by# t dh t as t wbp t wp note: ba= block address downloaded from: http:///
?2015 ds-20005015b 08/15 40 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs figure 11: data# polling timing diagram figure 12: toggle bits timing diagram 1309 f06.1 address a ms-0 dq 7 data data # data # data we# oe# ce# t oeh t oe t ce t oes note: a ms = most significant address a ms = a 21 for sst38vf6401/6402/6403/6404 1309 f07.0 address a ms-0 dq 6 and dq 2 we# oe# ce# t oe t oeh t ce t oes two read cycles with same outputs note: a ms = most significant address a ms = a 21 for sst38vf6401/6402/6403/6404 downloaded from: http:///
?2015 ds-20005015b 08/15 41 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs figure 13: we# controlled chip-erase timing diagram 1309 f08.1 address a ms-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 555 2aa 2aa 555 555 xx55 xx10 xx55 xxaa xx80 xxaa 555 oe# ce# ry/by# t wp six-byte code for chip-erase t sce t busy note: this device also supports ce# controlled ch ip-erase operation the we# and ce# signals are interchangeable as long as minimum timings are met. (see table 24) a ms = most significant address a ms = a 21 for sst38vf6401/6402/6403/6404 wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. downloaded from: http:///
?2015 ds-20005015b 08/15 42 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs figure 14: we# controlled block-erase timing diagram 1309 f09.1 address a ms-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 555 2aa 2aa 555 555 xx55 xx30 xx55 xxaa xx80 xxaa ba x oe# ce# t busy ry/by# t be six-byte code for block-erase t wp note: this device also supports ce# controlled block-erase operation the we# and ce# signals are interchangeable as long as minimum timings are met. (see table 24) ba x = block address a ms = most significant address a ms = a 21 for sst38vf6401/6402/6403/6404 wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. downloaded from: http:///
?2015 ds-20005015b 08/15 43 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs figure 15: we# controlled sector-erase timing diagram 1309 f10.1 address a ms-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 555 2aa 2aa 555 555 xx55 xx50 xx55 xxaa xx80 xxaa sa x oe# ce# six-byte code for sector-erase t se ry/by# t busy t wp note: this device also supports ce# cont rolled sector-erase operation the we# and ce# signals are interchangeable as long as minimum timings are met. (see table 24) sa x = sector address a ms = most significant address a ms = a 21 for sst38vf6401/6402/6403/6404 wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value. downloaded from: http:///
?2015 ds-20005015b 08/15 44 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs figure 16: software id entry and read figure 17: cfi query entry and read 1309 f11.0 address a ms-0 t ida dq 15-0 we# sw0 sw1 sw2 555 2aa 555 0000 0001 oe# ce# three-byte sequence for software id entry t wp t wph t aa 00bf device id xx55 xxaa xx90 note: device id = 536b for sst38vf6401, 536a for sst38vf6402, 536d for sst38vf6403, 536c for sst38vf6404 a ms = most significant address a ms = a 21 for sst38vf6401/6402/6403/6404 wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value. 1309 f12.2 address a ms-0 t ida dq 15-0 we# 55h oe# ce# t wp t aa 98h note: wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. a ms = most significant address a ms = a 21 for sst38vf6401/6402/6403/6404 downloaded from: http:///
?2015 ds-20005015b 08/15 45 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs figure 18: software id exit/cfi exit figure 19: sec id entry 1309 f13.0 address a ms-0 dq 15-0 t ida t wp t whp we# sw0 sw1 sw2 555 2aa 555 three-byte sequence for software id exit and reset oe# ce# xxaa xx55 xxf0 note: wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. a ms = most significant address a ms = a 21 for sst38vf6401/6402/6403/6404 1309 f14.1 address a ms-0 t ida dq 15-0 we# sw0 sw1 sw2 555 2aa 555 oe# ce# three-byte sequence for sec id entry t wp t wph t aa xx55 xxaa xx88 note: a ms = most significant address a ms = a 21 for sst38vf6401/6402/6403/6404 wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value. downloaded from: http:///
?2015 ds-20005015b 08/15 46 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs figure 20: rst# timing diagram (when no internal operation is in progress) figure 21: rst# timing diagram (during program or erase operation) figure 22: ac input/output reference waveforms 1309 f15.2 rst# ce#/oe# t rp t rhr t ry ry/by# 1309 f16.2 rst# ce#/oe# t rp t rye ry/by# t rb 1309 f17.0 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. mea- surement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test downloaded from: http:///
?2015 ds-20005015b 08/15 47 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs figure 23: a test load example 1309 f18.1 to tester to dut c l v dd 25k 25k downloaded from: http:///
?2015 ds-20005015b 08/15 48 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs figure 24: word-program algorithm 1309 f19.1 start load data: xxaah address: 555h load data: xx55h address: 2aah load data: xxa0h address: 555h load word address word data wait for end of program program complete note: x can be v il or v ih, but no other value. downloaded from: http:///
?2015 ds-20005015b 08/15 49 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs figure 25: write-buffer programming 1309 f25.2 start load data: xxaah address: 555h load data: xx55h address: 2aah load data: xx25h address: ba wait for end of program program complete load data: wc address: ba load data: data address: wa program buffer to flash load data: xx29h address: ba is data load complete? ye s no keep writing to buffer note: ba= block address wc = word count wa = address of word to program all subsequent address values (wa x ) in write cycle 6 and later must have the same a 21 -a 4 as wa x in write cycle 5. x can be v il or v ih, but no other value downloaded from: http:///
?2015 ds-20005015b 08/15 50 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs figure 26: wait options 1309 f20.1 wait t bp , t wbp , t sce, t se or t be program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same word data# polling program/erase completed program/erase completed read word is dq 7 = true data? read dq 7 program/erase initiated program/erase initiated ye s no ry/by# program/erase completed is ry/by# = 1? read ry/by# program/erase initiated note: for a program buffer-to-flash operation, the valid dq 7 is from the last word loaded in the buffer using the write- to-program buffer command. downloaded from: http:///
?2015 ds-20005015b 08/15 51 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs figure 27: cfi/sec id/software id entry command flowcharts 1309 f21.0 load data: xxaah address: 555h software product id entry command sequence load data: xx55h address: 2aah load data: xx90h address: 555h wait t ida read software id cfi query entry command sequence load data: xx98h address: 555h wait t ida read cfi data load data: xxaah address: 555h sec id entry command sequence load data: xx55h address: 2aah load data: xx88h address: 555h wait t ida read sec id note: x can be v il or v ih, but no other value. downloaded from: http:///
?2015 ds-20005015b 08/15 52 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs figure 28: software id/cfi/sec id exit command flowcharts 1309 f26.2 sec id exit command sequence software id exit command sequence cfi exit command sequence load data: xxaah address: 555h load data: xx55h address: 2aah load data: xxf0h address: 555h wait t ida return to normal operation load data: xxf0h address: xxh wait t ida load data: xxaah address: 555h load data: xx55h address: 2aah load data: xx90h address: 555h load data: xx00h address: xxxh wait t ida return to normal operation return to normal operation note: x can be v il or v ih, but no other value. downloaded from: http:///
?2015 ds-20005015b 08/15 53 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs figure 29: erase command sequence 1309 f23.0 load data: xxaah address: 555h chip-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx10h address: 555h load data: xxaah address: 555h wait t sce chip erased to ffffh load data: xxaah address: 555h sector-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx50h address: sa x load data: xxaah address: 555h wait t se sector erased to ffffh load data: xxaah address: 555h block-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx30h address: ba x load data: xxaah address: 555h wait t be block erased to ffffh note: x can be v il or v ih, but no other value. ba= block address sa = sector address downloaded from: http:///
?2015 ds-20005015b 08/15 54 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs figure 30: erase suspend/resume 1309 f27.0 start erase operation load data: xxb0h address: xxxh wait time (20 s max ) erase suspend active execute valid operations while in erase suspend mode load data: xx30h address: xxxh resume erase operation note: x can be v il or v ih, but no other value. downloaded from: http:///
?2015 ds-20005015b 08/15 55 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs figure 31: volatile block protection 1309 f28.3 load data: xxaah address: 555h load data: xx55h address: 2aah load data: xxe0h address: 555h wait t ida load data: xxa0h address: 555h load data: data address: ba load data: xx90h address: xxxh load data: xx00h address: xxxh read data: data address: ba more blocks to protect/unprotect or read status? ye s no read protect status protect / unprotect note: data = 00h (unprotect); data = 01h (protect). ba = block address x can be v il or v ih, but no other value. downloaded from: http:///
?2015 ds-20005015b 08/15 56 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs figure 32: non-volatile block protect mode program (protect block) load data: xxaah address: 555h load data: xx55h address: 2aah load data: xxc0h address: 555h wait t ida load data: xx80h address: xxh read data: data address: ba load data: xxa0h address: xxh load data: xx30h address: 00h wait for end of program, erase, or read load data: xx90h address: xxh load data: xx00h address: xxh load data: xx00h address: ba more to program,erase, or read? erase read protect status ye s no 1309 f30.1 program, erase or read note: data = 00h (unprotect); data = 01h (protect). x can be v il or v ih, but no other value. downloaded from: http:///
?2015 ds-20005015b 08/15 57 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs figure 33: global lock of nvpbs set load data: xxaah address: 555h load data: xx55h address: 2aah load data: xx50h address: 555h wait t ida read data: status data address: xxxh load data: xxa0h address: xxh load data: xx90h address: xxh load data: xx00h address: xxh load data: xx00h address: xxh read status 1309 f31.0 note: status data: dq0 = 0 (locked); dq0 = 1 (unlocked). x can be v il or v ih, but no other value. downloaded from: http:///
?2015 ds-20005015b 08/15 58 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs figure 34: password operations (program, read, submit) program load data: xxaah address: 555h load data: xx55h address: 2aah load data: xx60h address: 555h wait t ida read data: status data address: pwa x load data: xxa0h address: xxh load data: xx90h address: xxh load data: xx00h address: xxh load data: pwd x address: pwa x read 1309 f32.0 more to program or read? ye s no load data: xxaah address: 555h load data: xx55h address: 2aah load data: xx60h address: 555h load data: xx25h address: 00h load data: xx03h address: 00h load data: pwd0 address: pwa0 load data: xx29h address: 00h wait 2 s wait t ida load data: pwd1 address: pwa1 load data: pwd2 address: pwa2 load data: pwd3 address: pwa3 load data: xx90h address: xxh load data: xx00h address: xxh exit password command mode submit password program / read password note: the pwdx and pwax data and address pairs can be submitted in any order. downloaded from: http:///
?2015 ds-20005015b 08/15 59 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs figure 35: irreversible block lock in main array load data: aah address: 555h load data: 55h address: 2aah load data: 8 7h address: 555h load data: 00h address: xxh 1309 f33.0 note: global lock bit must be ?1? before executing this command. x can be v il or v ih, but no other value. downloaded from: http:///
?2015 ds-20005015b 08/15 60 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs product ordering information sst 38 vf 6401 - 90 - 5c - eke xx xx xxxx -xx -xx - xxx environmental attribute e 1 = non-pb package modifier k = 48 balls or leads package type e = tsop (type1, die up, 12mm x 20mm) b3 = tfbga (6mm x 8mm, 0.8mm pitch) temperature range c = commercial = 0c to +70c i = industrial = -40c to +85c minimum endurance 5 = 100,000 cycles read access speed 90 = 90 ns hardware block protection 1 = bottom boot-block uniform (32 kword) 2 = top boot-block uniform (32 kword) 3 = bottom boot-block non-uniform(8 kword) 4 = top boot-block non-uniform (8 kword) device density 640 = 64 mbit voltag e v = 2.7-3.6v product series 38 = advanced multi-purpose flash plus 1. environmental suffix ?e? denotes non-pb solder. non-pb solder devices are ?rohs compliant?. downloaded from: http:///
?2015 ds-20005015b 08/15 61 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs valid combinati ons for sst38vf6401 valid combinati ons for sst38vf6402 valid combinati ons for sst38vf6403 valid combinati ons for sst38vf6404 note: valid combinations are those products in mass producti on or will be in mass production. consult your sales representative to confirm availability of valid comb inations and to determine availability of new combina- tions. sst38vf6401-90-5c-eke sst38vf6401-90-5c-b3ke sst38vf6401-90-5i-eke sst38vf6401-90-5i-b3ke sst38vf6402-90-5c-eke sst38vf6402-90-5c-b3ke sst38vf6402-90-5i-eke sst38vf6402-90-5i-b3ke sst38vf6403-90-5c-eke sst38vf6403-90-5c-b3ke sst38vf6403-90-5i-eke sst38vf6403-90-5i-b3ke sst38vf6404-90-5c-eke sst38vf6404-90-5c-b3ke sst38vf6404-90-5i-eke sst38vf6404-90-5i-b3ke downloaded from: http:///
?2015 ds-20005015b 08/15 62 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs packaging diagrams figure 36: 48-lead thin small outline package (tsop) 12mm x 20mm package code: eke for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: microchip technology drawing c04-14036a sheet 1 of 1 48-lead thin small outline package (eke/f) - [tsop] 48-tsop-ek-8 note: 1. complies with je dec publication 95 mo-142 dd dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (max/min). 3. coplanarity: 0.1 mm 4. maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. downloaded from: http:///
?2015 ds-20005015b 08/15 63 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs figure 37: 48-ball thin-profile, fine-pitch ba ll grid array (tfbga) 6mm x 8mm package code: b3ke for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: microchip technology drawing c04-14035a sheet 1 of 1 48-lead thin fine-pitch ball grid array (b3ke/f) - 6x8 mm body [tfbga] 48-tfbga-b3k-6x8-450mic-5 note: 1. complies with jedec publication 95, mo-210, variant 'ab-1', although some dimensions may be more stringent. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.12 mm 4. ball opening size is 0.38 mm ( 0.05 mm) downloaded from: http:///
?2015 ds-20005015b 08/15 64 64 mbit (x16) advanced multi-purpose flash plus sst38vf6401 / sst38vf6402 / sst38vf6403 / sst38vf6404 not recommended for new designs table 25: revision history number description date 00 ? initial release mar 2007 01 ? removed program suspend/resume on page 10 ? updated ?erase-suspend/erase-resume commands? on page 11 ? updated ?non-volatile block protection? on page 19 ? updated ?password mode (dq 2 , dq 1 = 0,1)? on page 20 ? updated ?power-up specifications? on page 32 ? added a note to figure 32 on page 56 ? updated ?product ordering information? on page 60 sep 2007 02 ? modified features and product description on page 1 dec 2007 03 ? revised endurance statement in features, product description and table 20 footnote ? updated ?product ordering information? on page 60 ? changed document status to ?preliminary specification? aug 2008 04 ? changed 1v per 100 s to 1v per 100 ms in power up specification on page 26 jan 2009 05 ? eol of all 10,000 cycle endurance products. all 10,000 cycle endurance products removed. see s71309(01). ? changed document status to ?data sheet? jul 2009 a ? applied new document format ? released document under letter-revision system ? updated spec number from s71309 to ds-25015 apr 2011 b ? document marked ?not recommended for new designs.? aug 2015 ? 2015 microchip technology inc. sst, silicon storage technology, the sst logo, superflash, and mtp are registered trademarks of microchip technology, inc. mpf, sqi, serial quad i/o, and z-scale are trademarks of microc hip technology, inc. all other trademarks and registered trade- marks mentioned herein are the property of their respective owners. specifications are subject to change without notice. refer to www.microchip.com for th e most recent documentation. for the most current package drawings, please see the packaging specific ation located at http://www.microchip.com/packaging. memory sizes denote raw storage capacity ; actual usable capacity may be less. microchip makes no warranty for the use of its products other than those expressly contained in the standard terms and conditio ns of sale. for sales office locations and information, please see www.microchip.com. www.microchip.com isbn:978-1-63277-711-9 downloaded from: http:///

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